Add a reference to the missing PCIe clock managed by this IP. The
clock resides in the south bridge.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20190627125245.26788-5-miquel.raynal@bootlin.com


Signed-off-by: Stephen Boyd <sboyd@kernel.org>