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Matthew Gerlach authored
This patch adds a Device Feature List (DFL) bus driver for the Altera SPI Master controller. The SPI master is connected to an Intel SPI Slave to Avalon Bridge inside an Intel MAX10 BMC Chip. Signed-off-by:
Matthew Gerlach <matthew.gerlach@linux.intel.com> Link: https://lore.kernel.org/r/20210416165720.554144-3-matthew.gerlach@linux.intel.com Signed-off-by:
Mark Brown <broonie@kernel.org>
Matthew Gerlach authoredThis patch adds a Device Feature List (DFL) bus driver for the Altera SPI Master controller. The SPI master is connected to an Intel SPI Slave to Avalon Bridge inside an Intel MAX10 BMC Chip. Signed-off-by:
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