The LCD clock dividers are apparently based on one. No datasheet,
determined empirically, but seems to be confirmed by line 19 of lcd.fth in
OLPC laptop's Open Firmware [1]:

   h# 00000700 value pmua-disp-clk-sel  \ PLL1 / 7 -> 113.86 MHz

[1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth



Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk


Signed-off-by: Stephen Boyd <sboyd@kernel.org>