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Damien Le Moal authored
The Canaan Kendryte K210 RISC-V SoC includes a DW apb_ssi v4 controller which is documented to have a 32 words deep TX and RX FIFO. The FIFO length detection in spi_hw_init() correctly detects this value. However, when the controller RX FIFO is filled up to 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. This likely due to a hardware bug which can be avoided by force setting the fifo_len field of struct dw_spi to 31. Define the dw_spi_canaan_k210_init() function to force set fifo_len to 31 when the device node compatible string is "canaan,k210-spi". Signed-off-by:
Damien Le Moal <damien.lemoal@wdc.com> Acked-by:
Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20201206011817.11700-4-damien.lemoal@wdc.com Signed-off-by:
Mark Brown <broonie@kernel.org>
Damien Le Moal authoredThe Canaan Kendryte K210 RISC-V SoC includes a DW apb_ssi v4 controller which is documented to have a 32 words deep TX and RX FIFO. The FIFO length detection in spi_hw_init() correctly detects this value. However, when the controller RX FIFO is filled up to 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. This likely due to a hardware bug which can be avoided by force setting the fifo_len field of struct dw_spi to 31. Define the dw_spi_canaan_k210_init() function to force set fifo_len to 31 when the device node compatible string is "canaan,k210-spi". Signed-off-by:
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